SMIs Are EEEEVIL (Part 2)

In Part 1, I discussed a bit of the history and function of SMIs.  How does this make them EEEEVIL, is the question? Essentially, SMIs are the final word in what happens on a CPU, outside of removing power.  They cannot be interrupted, even by a Non-Maskable Interrupt (NMI).  Also, since they are not assertable…

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SMIs Are EEEEVIL (Part 1)

As a quick introduction, SMIs were introduced to the x86 world by the 386SL.  It was created to allowed systems designers to have access to the CPU while unspecified software of any type was running.  The reasons for this are obvious when you look at the market the 386SL was aimed it.  It was Intel’s…

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Favorite Hardware Bugs <CENSORED>

Want to know why I started posting again just now?  Adi Oltean posted a great entry about his favorite hardware bug.  This prompted Larry Osterman to post his favorite, and I started feeling left out.  I have a ton to choose from, after all I deal with new bleeding edge hardware on a daily basis. I’m…

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Back from a long hiatus

Well, I sort of had to stop blogging for awhile there because I moved on to a slightly different role.  I have the same job at the end of the day, but now I support more general portions of the OS, and of course one of the things I enjoy most: storage.  This has always been…

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